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Syllabus 2022-23 - 74212006 - Complex Digital Systems Design (Diseño de sistemas digitales complejos)
- Level 1: Tutorial support sessions, materials and exams in this language
- Level 2: Tutorial support sessions, materials, exams and seminars in this language
- Level 3: Tutorial support sessions, materials, exams, seminars and regular lectures in this language
DEGREE: | Máster en Ingeniería de Telecomunicación |
FACULTY: | SCHOOL OF ENGINEERING OF LINARES |
ACADEMIC YEAR: | 2022-23 |
COURSE: | Complex Digital Systems Design |
NAME: Complex Digital Systems Design | |||||
CODE: 74212006 | ACADEMIC YEAR: 2022-23 | ||||
LANGUAGE: English | LEVEL: 3 | ||||
ECTS CREDITS: 6.0 | YEAR: 1 | SEMESTER: PC |
NAME: MUÑOZ DÍEZ, JOSÉ VICENTE | ||
DEPARTMENT: U133 - ING. ELECTRÓNICA Y AUTOMATICA | ||
FIELD OF STUDY: 785 - TECNOLOGÍA ELECTRÓNICA | ||
OFFICE NO.: D - 115 | E-MAIL: jmunoz@ujaen.es | P: 953 648635 |
WEBSITE: jmunoz@ujaen.es | ||
ORCID: https://orcid.org/0000-0001-6190-7077 | ||
LANGUAGE: English | LEVEL: 3 | |
NAME: NIETO NIETO, LUIS MIGUEL | ||
DEPARTMENT: U133 - ING. ELECTRÓNICA Y AUTOMATICA | ||
FIELD OF STUDY: 785 - TECNOLOGÍA ELECTRÓNICA | ||
OFFICE NO.: - | E-MAIL: - | P: - |
WEBSITE: - | ||
ORCID: https://orcid.org/0000-0001-8013-9528 | ||
LANGUAGE: English | LEVEL: 3 |
- History of Configurable Digital Circuits
- Introduction to FPGA Design
- Introduction
- Background of the CDCs (PLDs)
- Definition and classification of Configurable Digital Circuits
- Main Features
- Design phases with CDCs
- Advantages of CDCs
- Applications
- Basic theory on FPGAs
- Introduction to FPGAs
- FPGA Architectures
- Logical resources
- Basic internal logic blocks
- Blocks input / output
- Dedicated circuits
- Interconnection resources
- Interconnection lines
- Configurable connections
- Characteristics of FPGAs
- FPGA Technology
- Introduction
- Setup Memory
- Configuration Technology
- EEPROM technology passive
- Active Memory SRAM Technologies
- Antifuse Technologies
- Configuration Methods
- Comparative
- FPGAs verification
- Stages of design with FPGAs
- Overview
- Stages of design and implementation of a digital system using FPGAs
- Design Overview
- Compilation and synthesis
- Implementation
- Programming circuit
- Verification
- CAD tools
- Architecture of FPGAs Altera Cyclone family
- Overview
- Cyclone subfamilies of the family
- Basic Architecture
- Internal logic resources
- Clock circuit
- Resource input / output (I / S)
- Interconnection resources
- Cyclone II subfamily
- Other common features
- Electrical and temporal characteristics
- Design Standards
- Introduction to the design method of digital systems with
FPGAs
- Overview
- Digital Systems Design
- Coupling between FPGAs and other components, circuits and
systems
- Overview
- Switches and pushbuttons
- LEDs
- 7-segment displays
- Circuits
- 3-state Buses
- Timers
- D / A Converter
- A / D Converter
- Memories
- Microprocessors and Microcontrollers
- Communication Interfaces
- Synchronous Design with FPGAs
- Overview
- SSS: Design standards with FPGAs
- Transient outputs
- Helpful Tools
- Applications of FPGAs
- Scope
- Fields of application
- Types of circuits implemented
- Characteristics of FPGAs
- Examples of actual application
- Application Analysis
- Introduction to the design of complex digital systems
- Sync entries
- Overview
- Synchronization of input variables
- Asynchronous Independent Variables
- Edge Detection
- Variables related asynchronous
- Variables with its own clock signal
- Variables autosynchronized
- S.S.S. with different clocks
- Detecting short pulses
- Analysis of delays of digital systems
- Overview
- Delay types
- Reports on delays
- Analysis of delays
- Delays of a S.S.S. control
- Calculation examples
- Tutorial Design with FPGAs in Altera Quartus II tools
- Overview
- Creating projects
- Description using VHDL
- RTL Viewer
- Altera Library. Configurable components
- Compilation. Synthesis. Viewef.
- Functional simulation
- Implementation
- Simulation over time
- Board test
- Programming the circuit
- Advanced Design Techniques
- Overview
- Digital systems design:
- Hierarchical design. incremental compilation
- Design transferable to other technologies
The development of large group and small group lectures will be focused on promoting quality teaching by giving priority to activities that foster inclusive and equitable learning (SDG-4). According to this, the methodology followed in this subject are based on six main points:
1) Lessons and seminars. It means master lectures delivered
by the professor where the active participation of the students is
going to be boosted.
2) Practical lessons. These lessons will be delivered in the
laboratory in groups where the maximum number of students per group
will not be more than 20 people. These lessons will allow to put in
practice the concepts which will be described through the
theoretical lessons.
3) Resolution of the problems proposed in class. These
problems will be focused on aspects dealt in theoretical and
practical sessions.
4) Tutorial sessions in group or individual. This activity
will allow to give a more personal answer to the doubts that the
students will have along the academic year.
5) Oral presentations in class performed by the students. The presentations will deal with wide range of topics related to the subject. The aim of this activity is to give the students the chance for going further on their own in those topics of the subject that they find more applealing.
6) Exams resolution by which the students knowledge will be evaluated.
Students with special educational needs should contact the Student Attention Service (Servicio de Atención y Ayudas al Estudiante) in order to receive the appropriate academic support
The evaluation of the subject is based on the mark obtained in
two parts:
1) Practical problems resolution with attendance and active
participation in tutorial lectures. There will be practical
sessions which will take place in the laboratory. In same of them
could be needed to submit a final report. The score obtained in
this part will represent 50% of the overall mark.
2) Students knowledge will be evaluated by means written
exams and presentations in class. The mark obtained in this part
will represent 50% of the overall mark.
The first point described above is aimed to evaluate the progress of the students in order to achieve the competences CB10, CB8, CB9, CE11, CE12, CG10, CG8, CG9, CT3, CT4, CT5, CT6 and CT7. Moreover, the following results of the learning are also evaluated by this activity: Resul-21, Resul-22, Resul-23, Resul-24, Resul-25 and Result-26.
The second point described above is aimed to evaluate the progress of the students in order to achieve the competences CE11, CE12 and CT4. Moreover, the following results of the learning are also evaluated by this activity: Resul-21, Resul-24 and Result-25.
Note: There is not a minimum mark (for any of the points above described) that the students have to achieve to compute the average of the two parts (overall mark). However, for the exam which takes place in July is necessary to get a mark higher than 4.5 point (out of 10) for each part to compute the overall mark.
- Digital electronics with VHDL, Quartus II version . Edition: -. Author: Kleitz, William. Publisher: Upper Saddle River, N.J. : Pearson Prentice Hall, c2006 (Library)
- Beginning FPGA: Programming Metal [electronic resource] : Your brain on hardware . Edition: 1st ed. 2017.. Author: Pang, Aiken. author.. Publisher: Apress (Library)
- Digital systems design with FPGAs and CPLDs . Edition: -. Author: Grout, Ian.. Publisher: Elsevier Newnes (Library)
- Rapid Prototyping of Digital Systems [electronic resource] : SOPC Edition . Edition: 1st ed. 2008.. Author: Hamblen, James O. author.. Publisher: Springer US (Library)
- FPGA prototyping by VHDL examples [electronic resource] : Xilinx Spartan-3 version . Edition: -. Author: Chu, Pong P., 1959-. Publisher: Wiley-Interscience (Library)
Due to the short number of students usually enrolled in the master the lessons for all the students will take place in the indicated classroom. So, any access restriction restriction will be applied.
Teaching Activities
and Methodologies
Teaching
activities
|
Format |
Methodologies |
Theoretical lectures for all the students which will last 1 hour |
Online and synchronous |
Online Masterclass
|
Practical sessions for
all the students in laboratory which will last 2 hours
|
Online and synchronous |
Online practical sessions which will include seminars and simulations tools for electronic circuits |
Tutorial lectures |
Online |
By any available online platform |
Assessment
OVERALL ASSESSMENT |
|||
Kind of test |
Tool |
Description |
Weigth |
S1. Active participation in lectures and tutorials. - Active participation in lab work. -Attendance to individual tutorial and activities. |
Observation and problems resolution |
-Active participation in lectures and tutorials. - Active participation in lab oratory work. -Attendance to individual tutorial and activities. |
10 % |
S2. Practical and theoretical assimilation of subject concepts. |
Practical and theoretical assimilation of subject concepts. |
Online written exam according to the official schedule |
50 % |
S10. Design and
implementation of digital complex circuits
|
Designing and simulation of the proposed practical examples |
-Documentation delivered. The revision for each document includes: -Structure - Quality - Novelty - Clarity of presentation |
4 0 % |
The mark for S10 in the extra exam session will be assessed by a practical exam if any . Nevertheless, a mark up to 4 in S2 will be necessary to proceed to the computation of the overall mark (computing as the average of the available ones ). The weigths will be modified due to the fact that S1 mark is not applicable in the extra exam session, so only S2 (50%) and S10 (50%) will be computed. The student will pass the course in case they get a overall mark in exceed of 5. |
Single Exam* |
|||
Test |
Tool |
Description |
Weight |
S2. Practical and theoretical assimilation of subject concepts. |
Practical and theoretical assimilation of subject concepts. |
Online written exam |
50% |
S10. Design and
implementation of digital complex circuits
|
Designing and simulation of the proposed practical examples |
-Documentation delivered. The revision for each document includes: -Structure - Quality - Novelty - Clarity of presentation |
50% |
At the very least a mark of 4.5 in S2 and S10 will be needed to compute the overall mark. The student will pass the course in case they get a overall mark in exceed of 5. |
* According to the article 13 th of the Official Academic Guideline for the assessment of the Students at the University of Jaen whoever student has the right to ask for this exam as long as they justify the reason why the can not take part in regular teaching activities. They must let the professor know about it a week in advance the beginning of the exam period.
Resources
The communication means will be profoundly modified under this scenario. Thus, the following resources will be used:
Video call on Google Meet o whatever similar platform .
Virtual blackboard by Google Jamboard o r similar.
Resources available on ILIAS platform .
Institution in charge of data processing: Universidad de Jaén, Campus Las Lagunillas, s/n, 23071 Jaén
Data Protection Delegate: dpo@ujaen.es
Purpose: In accordance with the Universities Law and other national and regional regulations in force, carrying out exams and assessment tests corresponding to the courses students are registered in. In order to avoid frauds while sitting the exam, the exam will be answered using a videoconference system, being able the academic staff of the University of Jaén to compare and contrast the image of the person who is answering the exam with the student's photographic files. Likewise, in order to provide the exam with evidential content for revisions or claims, in accordance with current regulation frameworks, the exam will be recorded and stored.
Legitimacy: compliance with legal obligations (Universities Law) and other national and regional regulations currently in force.
Addressees: service providers who are the owners of the platforms where the exams are carried out and with whom the University of Jaén has signed the corresponding data access contracts.
Storage periods: those established in current in force regulations. In the specific case of exam videoconference recordings, not before the examination records and transcripts are closed or the exam can still be reviewed or challenged.
Rights: you can exercise your right of access, amendment, cancellation, opposition, suppression, limitation and portability by sending a letter to the postal or electronic address indicated above. In the event that you consider that your rights have been violated, you may submit a complaint to the Andalusian Council for Transparency and Data Protection www.ctpdandalucia.es
Person in charge: Universidad de Jaén, Paraje Las Lagunillas, s/n; Tel.953 212121; www.ujaen.es
Data protection delegate (DPO): TELEFÓNICA, S.A.U. ; Email: dpo@ujaen.es
Procedure aim: To manage proper recordings of teaching sessions with the aim of facilitating learning process under a multimodal and/or online teaching
Period for record storage: Images will be kept during legal term according to regulations in force
Legitimacy: Data will be managed according to legal regulations (Organic Law 6/2001, December 21, on Universities) and given consent provided by selecting corresponding box in legal admission documents
Data recipients (transfers or assignments): Any person allowed to get access to every teaching modality
Rights: You may exercise your rights of access, rectification, cancellation, portability, limitation of processing, deletion or, where appropriate, opposition. To exercise these rights, you must submit a written request to the Information, Registration and Electronic Administration Service of the University of Jaen at the address above, or by e-mail to the address above. You must specify which of these rights you are requesting to be satisfied and, at the same time, you must attach a photocopy of your ID card or equivalent identification document. In case you act through a representative, legal or voluntary, you must also provide a document that proves this representation and identification. Likewise, if you consider that your right to personal data protection has been violated, you may file a complaint with the Andalusian Data Protection and Transparency Council www.ctpdandalucia.es