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Syllabus 2019-20 - 74212006 - Complex Digital Systems Design (Diseño de sistemas digitales complejos)

Caption
  • Level 1: Tutorial support sessions, materials and exams in this language
  • Level 2: Tutorial support sessions, materials, exams and seminars in this language
  • Level 3: Tutorial support sessions, materials, exams, seminars and regular lectures in this language
DEGREE: Máster en Ingeniería de Telecomunicación
FACULTY: SCHOOL OF ENGINEERING OF LINARES

ACADEMIC YEAR: 2019-20
SYLLABUS
1. COURSE BASIC INFORMATION
NAME: Complex Digital Systems Design
CODE: 74212006 ACADEMIC YEAR: 2019-20
LANGUAGE: English LEVEL: 3
ECTS CREDITS: 6.0 YEAR: 1 SEMESTER: PC
 
2. LECTURER BASIC INFORMATION
NAME: MUÑOZ DÍEZ, JOSÉ VICENTE
DEPARTMENT: U133 - ING. ELECTRÓNICA Y AUTOMATICA
FIELD OF STUDY: 785 - TECNOLOGÍA ELECTRÓNICA
OFFICE NO.: D - 115 E-MAIL: jmunoz@ujaen.es P: 953 648635
WEBSITE: jmunoz@ujaen.es
LANGUAGE: English LEVEL: 3
 
NAME: NIETO NIETO, LUIS MIGUEL
DEPARTMENT: U133 - ING. ELECTRÓNICA Y AUTOMATICA
FIELD OF STUDY: 785 - TECNOLOGÍA ELECTRÓNICA
OFFICE NO.: D - 116 E-MAIL: lmnieto2@ujaen.es P: 953648668
WEBSITE: http:\\www4.ujaen.es\~lmnieto2
LANGUAGE: English LEVEL: 3
 
3. CONTENT DESCRIPTION

 

  • History of  Configurable Digital Circuits
  • Introduction to FPGA Design
    • Introduction
    • Background of the CDCs (PLDs)
    • Definition and classification of Configurable Digital Circuits
    • Main Features
    • Design phases with CDCs
    • Advantages of CDCs
    • Applications
  • Basic theory on FPGAs
    • Introduction to FPGAs
    • FPGA Architectures
    • Logical resources
      • Basic internal logic blocks
      • Blocks input / output
      • Dedicated circuits
    • Interconnection resources
      • Interconnection lines
      • Configurable connections
    • Characteristics of FPGAs
  • FPGA Technology
    • Introduction
    • Setup Memory
    • Configuration Technology
      • EEPROM technology passive
      • Active Memory SRAM Technologies
      • Antifuse Technologies
    • Configuration Methods
    • Comparative
    • FPGAs verification
  • Stages of design with FPGAs
    • Overview
    • Stages of design and implementation of a digital system using FPGAs
    • Design Overview
    • Compilation and synthesis
    • Implementation
    • Programming circuit
    • Verification
    • CAD tools
  • Architecture of FPGAs Altera Cyclone family
    • Overview
    • Cyclone subfamilies of the family
    • Basic Architecture
    • Internal logic resources
    • Clock circuit
    • Resource input / output (I / S)
    • Interconnection resources
    • Cyclone II subfamily
    • Other common features
    • Electrical and temporal characteristics
    • Design Standards
  • Introduction to the design method of digital systems with FPGAs
    • Overview
    • Digital Systems Design
  • Coupling between FPGAs and other components, circuits and systems
    • Overview
    • Switches and pushbuttons
    • LEDs
    • 7-segment displays
    • Circuits
    • 3-state Buses
    • Timers
    • D / A Converter
    • A / D Converter
    • Memories
    • Microprocessors and Microcontrollers
    • Communication Interfaces
  • Synchronous Design with FPGAs
    • Overview
    • SSS: Design standards with FPGAs
    • Transient outputs
    • Helpful Tools
  • Applications of FPGAs
    • Scope
    • Fields of application
    • Types of circuits implemented
    • Characteristics of FPGAs
    • Examples of actual application
    • Application Analysis
    • Introduction to the design of complex digital systems
  • Sync entries
    • Overview
    • Synchronization of input variables
      • Asynchronous Independent Variables
      • Edge Detection
      • Variables related asynchronous
      • Variables with its own clock signal
      • Variables autosynchronized
    • S.S.S. with different clocks
    • Detecting short pulses
  • Analysis of delays of digital systems
    • Overview
    • Delay types
    • Reports on delays
    • Analysis of delays
      • Delays of a S.S.S. control
      • Calculation examples
  • Tutorial Design with FPGAs in Altera Quartus II tools
    • Overview
    • Creating projects
    • Description using VHDL
    • RTL Viewer
    • Altera Library. Configurable components
    • Compilation. Synthesis. Viewef.
    • Functional simulation
    • Implementation
    • Simulation over time
    • Board test
    • Programming the circuit
  • Advanced Design Techniques
    • Overview
    • Digital systems design:
      • Hierarchical design. incremental compilation
      • Design transferable to other technologies

4. COURSE DESCRIPTION AND TEACHING METHODOLOGY

The methodology followed in this subject are based on six main didactic resources:


1) Lessons and seminars. It means master lectures delivered by the professor where the active participation of the students is going to be boosted.


2) Practical lessons. These lessons will be delivered in the laboratory in groups where the maximum number of students per group will not be more than 20 people. These lessons will allow to put in practice the concepts which will be described through the theoretical lessons.


3) Resolution of the problems proposed in class. These problems will be focused on aspects dealt in theoretical and practical sessions.


4) Tutorial sessions in group or individual. This activity will allow to give a more personal answer to the doubts that the students will have along the academic year.

5) Oral presentations in class performed by the students. The presentations will deal with wide range of topics related to the subject. The aim of this activity is to give the students the chance for going further on their own in those topics of the subject that they find more applealing.  

6) Exams resolution by which the students knowledge will be evaluated.

Students with special educational needs should contact the Student Attention Service (Servicio de Atención y Ayudas al Estudiante) in order to receive the appropriate academic support

5. ASSESSMENT METHODOLOGY

The evaluation of the subject is based on the mark obtained in two parts:

1) Practical problems resolution with attendance and active participation in tutorial lectures. There will be practical sessions which will take place in the laboratory. In same of them could be needed to submit a final report. The score obtained in this part will represent 50% of the overall mark.


2) Students knowledge will be evaluated by means written exams and presentations in class. The mark obtained in this part will represent 50% of the overall mark.

The first point described above is aimed to evaluate the progress of the students in order to achieve the competences CB10, CB8, CB9, CE11, CE12, CG10, CG8, CG9, CT3, CT4, CT5, CT6 and CT7. Moreover, the following results of the learning are also evaluated by this activity: Resul-21, Resul-22, Resul-23, Resul-24, Resul-25 and Result-26.

The second point described above is aimed to evaluate the progress of the students in order to achieve the competences CE11, CE12 and CT4. Moreover, the following results of the learning are also evaluated by this activity: Resul-21, Resul-24 and Result-25.

 

Note: There is not a minimum mark  (for any of the points above described) that the students have to achieve to compute the average of the two parts (overall mark). However, for the exam which takes place in July is necessary to get a mark higher than 5 point (over 10) for each part to pass the subject.

6. BOOKLIST
MAIN BOOKLIST:
  • Digital electronics with VHDL, Quartus II version . Edition: -. Author: Kleitz, William. Publisher: Upper Saddle River, N.J. : Pearson Prentice Hall, c2006  (Library)