Menú local
Syllabus 2016-17 - 74212006 - Complex Digital Systems Design (Diseño de sistemas digitales complejos)
- Level 1: Tutorial support sessions, materials and exams in this language
- Level 2: Tutorial support sessions, materials, exams and seminars in this language
- Level 3: Tutorial support sessions, materials, exams, seminars and regular lectures in this language
DEGREE: | Máster en Ingeniería de Telecomunicación |
FACULTY: | SCHOOL OF ENGINEERING OF LINARES |
ACADEMIC YEAR: | 2016-17 |
COURSE: | Complex Digital Systems Design |
NAME: Complex Digital Systems Design | |||||
CODE: 74212006 | ACADEMIC YEAR: 2016-17 | ||||
LANGUAGE: English | LEVEL: 3 | ||||
ECTS CREDITS: 6.0 | YEAR: 1 | SEMESTER: PC |
NAME: MUÑOZ DÍEZ, JOSÉ VICENTE | ||
DEPARTMENT: U133 - ING. ELECTRÓNICA Y AUTOMATICA | ||
FIELD OF STUDY: 785 - TECNOLOGÍA ELECTRÓNICA | ||
OFFICE NO.: D - 115 | E-MAIL: jmunoz@ujaen.es | P: 953 648635 |
WEBSITE: jmunoz@ujaen.es | ||
ORCID: https://orcid.org/0000-0001-6190-7077 | ||
LANGUAGE: English | LEVEL: 3 | |
NAME: NIETO NIETO, LUIS MIGUEL | ||
DEPARTMENT: U133 - ING. ELECTRÓNICA Y AUTOMATICA | ||
FIELD OF STUDY: 785 - TECNOLOGÍA ELECTRÓNICA | ||
OFFICE NO.: - | E-MAIL: - | P: - |
WEBSITE: - | ||
ORCID: https://orcid.org/0000-0001-8013-9528 | ||
LANGUAGE: English | LEVEL: 3 |
- History of Configurable Digital Circuits
- Introduction to FPGA Design
- Introduction
- Background of the CDCs (PLDs)
- Definition and classification of Configurable Digital Circuits
- Main Features
- Design phases with CDCs
- Advantages of CDCs
- Applications
- Basic theory on FPGAs
- Introduction to FPGAs
- FPGA Architectures
- Logical resources
- Basic internal logic blocks
- Blocks input / output
- Dedicated circuits
- Interconnection resources
- Interconnection lines
- Configurable connections
- Characteristics of FPGAs
- FPGA Technology
- Introduction
- Setup Memory
- Configuration Technology
- EEPROM technology passive
- Active Memory SRAM Technologies
- Antifuse Technologies
- Configuration Methods
- Comparative
- FPGAs verification
- Stages of design with FPGAs
- Overview
- Stages of design and implementation of a digital system using FPGAs
- Design Overview
- Compilation and synthesis
- Implementation
- Programming circuit
- Verification
- CAD tools
- Architecture of FPGAs Altera Cyclone family
- Overview
- Cyclone subfamilies of the family
- Basic Architecture
- Internal logic resources
- Clock circuit
- Resource input / output (I / S)
- Interconnection resources
- Cyclone II subfamily
- Other common features
- Electrical and temporal characteristics
- Design Standards
- Introduction to the design method of digital systems with
FPGAs
- Overview
- Digital Systems Design
- Coupling between FPGAs and other components, circuits and
systems
- Overview
- Switches and pushbuttons
- LEDs
- 7-segment displays
- Circuits
- 3-state Buses
- Timers
- D / A Converter
- A / D Converter
- Memories
- Microprocessors and Microcontrollers
- Communication Interfaces
- Synchronous Design with FPGAs
- Overview
- SSS: Design standards with FPGAs
- Transient outputs
- Helpful Tools
- Applications of FPGAs
- Scope
- Fields of application
- Types of circuits implemented
- Characteristics of FPGAs
- Examples of actual application
- Application Analysis
- Introduction to the design of complex digital systems
- Sync entries
- Overview
- Synchronization of input variables
- Asynchronous Independent Variables
- Edge Detection
- Variables related asynchronous
- Variables with its own clock signal
- Variables autosynchronized
- S.S.S. with different clocks
- Detecting short pulses
- Analysis of delays of digital systems
- Overview
- Delay types
- Reports on delays
- Analysis of delays
- Delays of a S.S.S. control
- Calculation examples
- Tutorial Design with FPGAs in Altera Quartus II tools
- Overview
- Creating projects
- Description using VHDL
- RTL Viewer
- Altera Library. Configurable components
- Compilation. Synthesis. Viewef.
- Functional simulation
- Implementation
- Simulation over time
- Board test
- Programming the circuit
- Advanced Design Techniques
- Overview
- Digital systems design:
- Hierarchical design. incremental compilation
- Design transferable to other technologies
Lectures will be delivered in the classroom with illustrative examples and exercises, using PowerPoint slides, video projections, etc. Afterward each example there will be a turn for questions where student cam ask questions and make suggestions to improve any aspect mentioned in the example. The active participation and the creativity of the students will be encouraged in the lectures
Students with special educational needs should contact the Student Attention Service (Servicio de Atención y Ayudas al Estudiante) in order to receive the appropriate academic support
The evaluation of the subject is based on three points:
1) Practical problems resolution and/or presentations in
class with attendance and active participation in tutorial
lectures. There will be practical/problem sessions which will be
corrected in the laboratory and another ones in which it will be
necessary to prepare a final report. This point will represent
32.5% of the final mark.
2) Design and implementation of an global project of the
subject. The topic of the project could be chosen by the students
or they will select another one proposed by the professors. This
point will represent 17.5% of the final mark.
3) Exams. This point will represent 50% of the final
mark.
The first point described above is aimed to evaluate the progress of the students in order to achieve the competences CB10, CB8, CB9, CE11, CE12, CG10, CG8, CG9, CT3, CT4, CT6 and CT7. Moreover, the following results of the learning are also evaluated by this activity: Resul-21, Resul-22, Resul-23, Resul-24, Resul-25 and Result-26.
The second point described above is aimed to evaluate the progress of the students in order to achieve the competences CB10, CB8, CB9, CE11, CE12, CG10, CG6, CG7, CG8, CG9, CT3, CT4, CT5, CT6 and CT7. Moreover, the following results of the learning are also evaluated by this activity: Resul-21, Resul-22, Resul-23, Resul-24, Resul-25 and Result-26.
The third point described above is aimed to evaluate the progress of the students in order to achieve the competences CE11, CE12 and CT4. Moreover, the following results of the learning are also evaluated by this activity: Resul-21, Resul-24 and Result-25.
Note: There is not a minimum mark (for any of the points above described) that the students have to achieve to compute the mean of the three parts (overall mark).
- Digital electronics with VHDL, Quartus II version . Edition: -. Author: Kleitz, William. Publisher: Upper Saddle River, N.J. : Pearson Prentice Hall, c2006 (Library)